1. Field of Invention
The invention relates generally to wireless communication and more particularly to an ultra wideband frequency synthesizer.
2. Related Prior Arts
The Federal Communication Commission (FCC) has reallocated 7.5 GHz unlicensed spectrum for ultra-wideband devices (UWB). UWB is emerging as a solution for the IEEE 802.15.3a standard. The purpose of this standard is to provide the features of a low complexity, low-cost, low power consumption, and high data-rate wireless connectivity for personal-area networks (PANs). Because FCC has made up the 3.1 to 10.6 GHz spectrum available for UWB applications, several methods have been proposed to come true high-rate short-range communication systems. Multi-band orthogonal frequency division multiplexing (MB-OFDM) is one of the proposals, which divides the allocated spectrum into quadrature phase shifted keying (QPSK) OFDM modulated sub-bands, each with a bandwidth of 528 MHz. A frequency-hopping scheme, in order to achieve efficient and robust communication, is applied to hop between carrier frequency bands. MB-OFDM defines a unique numbering system for all channels with spacing of 528 MHz. Based on this, five band groups are defined, consisting of four groups of three bands each and one group of two bands. Band group 1 (centered at 3432 MHz, 3960 MHz, and 4488 MHz) is used for Mode 1 devices (mandatory mode). The remaining band groups are reserved for future use, band group 2 of which contains 5016 MHz, 5544 MHz, and 6072 MHz. The MB-OFDM system switches frequency at the rate of the OFDM symbol. The frequency must settle within 9.5 ns. Conventional tunable phase-lock oscillators fail to provide such a fast switching due to their long settling time (>250 us). Alternatives are to generate carrier frequency by feeding output signals of phase locked loops (PLLs), which is also known as phase frequency detecting circuits, into single-sideband (SSB) mixer or selectors, or combination of both to form beat product for required channels. All of them have the same goals of fast switching on the order of nanoseconds and provides needed channels. It is indeed welcome to push cost and performance to the best at the same time if applicable.
Some attempts have been devised to provide high performance and low cost and they include:    (a) A 7-Band 3-8 GHz frequency synthesizer with 1 ns band-switching time in 0.18 um CMOS technology as illustrated in FIG. 1.            This frequency synthesizer generates clocks for 7 bands distributed from 3 to 8 GHz. As shown in FIG. 1, this architecture accommodates bands of Group A and Group C, which are defined in IEEE 802.15-03/267r5, with 2 PLLs, 102, 104, two selectors 106, 108, and one SSB mixer 110. Group PLL 102 generates the reference frequencies, 6864 MHz and 3432 MHz for Group A and C, whereas Band PLL 104 produces twofold the increment frequencies, 2112 MHz and 1056 MHz for frequency additions and subtractions. The feature of this design is that an additional programmable tri-mode buffer, capable of providing DC and quadrature signals with opposite I/Q sequences, is placed in front of one of inputs of the SSB mixer 110 so that the number of SSB mixers used deduces.            (b) A 0.13 um CMOS UWB Transceiver as illustrated in FIG. 2.            In a frequency synthesizer as shown in FIG. 2, the three local oscillator (LO) frequencies necessary for Mode 1 are produced by three fixed-modulus phase-locked loops 202 without using SSB mixers. The central frequency of each PLL 202 corresponds to each channel in band group 1, 3432 MHz, 3960 MHz, and 4488 MHz. Because of removal of SSB mixers, three PLLs 202 are needed to fix each channel frequency.            (c) A SiGe BiCMOS 1 ns Fast Hopping Frequency Synthesizer for UWB Radio as illustrated in FIG. 3.            This proposed multi-tone generator utilizes two quadrature PLLs 302, 304 to provide two fixed frequencies of 3960 MHz and 528 MHz, as displayed in FIG. 3. In order to match the Band group 1 requirement, PLL8G 302 output is taken as Band 2. Band 1 and Band 3 will be generated along with additions and subtractions by a SSB mixer 306 with an output from PLL2G 304 modified by increment frequency of 528 MHz. The divide-by-2 circuit 308 after voltage controlled oscillators (VCO) 310 is used to generate I/Q quadrature signals.        
However, each of these attempts has some shortcomings. For example:    (a) A 7-Band 3-8 GHz Frequency Synthesizer with 1 ns Band-Switching Time in 0.18 um CMOS Technology illustrated in FIG. 1.            The frequency synthesizer of FIG. 1 uses a minimum number of SSB mixers and selectors to demonstrate super fast switching at 1 ns between bands. The idea of two PLLs of Group PLL and Band PLL is nice to synthesize many channel bands with one more additional building block of Tri-Mode Buffer; however, a big area is consumed for inductor-capacitor VCO (LC-VCO) design in the PLLs 102, 104. Besides, an even worse case occurs when each VCO need to generate quadratrure signals, which means that a double space for inductors would be required.            (b) A 0.13 um CMOS UWB Transceiver illustrated in FIG. 2.            Although this circuit design looks good based on its performance, one thing needs to be focused on is that it uses three parallel PLLs 202 to focus on each channel frequency in Band group 1. That means, in the future, 14 PLLs may needed to cover the whole frequency range of MB-OFDM UWB communication bands from 3.1 to 10.6 GHz, if no SSB mixers and selectors are used. Furthermore, though ring oscillators, which are one type of VCO, are candidates for PLLs due to sensitivity degradation of 0.2 dB in the transceiver simulation, it might still be a very difficult challenge to generate 10.296 GHz for the 14th band channel by a typical design of a ring oscillator based tone generator. The phase noise associated with this ring oscillator PLLs 202 would be seriously unwanted. An additional inevitable disadvantage aroused from such design is that PLLs 202 need to stay in operation all the time. The power dissipation will be another big issue. In addition, if LC-VCO architecture is adapted for PLLs 202 to achieve higher resonant frequency, a huge amount of active die area is required for such frequency synthesizer design.            (c) A SiGe BiCMOS 1 ns Fast Hopping Frequency Synthesizer for UWB Radio illustrated in FIG. 3.            This frequency synthesizer uses dual-loop architecture with single-side band mixing to achieve the fast hopping characteristic. According to this design, use of one SSB mixer and one selector can provide only three channels in Band group 1. If more bands need to be covered for frequency hopping, such architecture may have to be modified. The purpose of placing a divide-by-2 after the VCOs is to bring out quadrature signal output for SSB mixers. Accordingly, with VCO resonant frequency doubled to operate in coordination to avoid using quadrature VCO results in more die area. Employing two PLLs to construct a Band group 1 frequency synthesizer is good but still occupies much die area.        
Therefore, it is to a frequency synthesizer design that involves less complexity and occupies less die area the present invention is primarily directed.